| Gated-V dd: a circuit technique to reduce leakage in deep-submicron cache memories M Powell, SH Yang, B Falsafi, K Roy, TN Vijaykumar Proceedings of the 2000 international symposium on Low power electronics and …, 2000 | 1138 | 2000 |
| Heat-and-run: leveraging SMT and CMP to manage power density through the operating system M Gomaa, MD Powell, TN Vijaykumar ACM SIGARCH Computer Architecture News 32 (5), 260-270, 2004 | 430 | 2004 |
| Optimizing replication, communication, and capacity allocation in CMPs Z Chishti, MD Powell, TN Vijaykumar 32nd International Symposium on Computer Architecture (ISCA'05), 357-368, 2005 | 423 | 2005 |
| Reducing set-associative cache energy via way-prediction and selective direct-mapping MD Powell, A Agarwal, TN Vijaykumar, B Falsafi, K Roy Proceedings of the 34th annual ACM/IEEE international symposium on …, 2001 | 370 | 2001 |
| An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches SH Yang, MD Powell, B Falsafi, K Roy, TN Vijaykumar High-Performance Computer Architecture, 2001. HPCA. The Seventh …, 2001 | 339 | 2001 |
| Distance associativity for high-performance energy-efficient non-uniform cache architectures Z Chishti, MD Powell, TN Vijaykumar Proceedings of the 36th annual IEEE/ACM International Symposium on …, 2003 | 296 | 2003 |
| Reducing register ports for higher speed and lower energy I Park, MD Powell, TN Vijaykumar Microarchitecture, 2002.(MICRO-35). Proceedings. 35th Annual IEEE/ACM …, 2002 | 211 | 2002 |
| Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay SH Yang, MD Powell, B Falsafi, TN Vijaykumar High-Performance Computer Architecture, 2002. Proceedings. Eighth …, 2002 | 206 | 2002 |
| Architectural core salvaging in a multi-core processor for hard-error tolerance MD Powell, A Biswas, S Gupta, SS Mukherjee ACM SIGARCH Computer Architecture News 37 (3), 93-104, 2009 | 168 | 2009 |
| Reducing leakage in a high-performance deep-submicron instruction cache M Powell, SH Yang, B Falsafi, K Roy, N Vijaykumar IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (1), 77-89, 2001 | 132 | 2001 |
| CAMP: A technique to estimate per-structure power at run-time using a few simple parameters MD Powell, A Biswas, JS Emer, SS Mukherjee, BR Sheikh, S Yardi 2009 IEEE 15th International Symposium on High Performance Computer …, 2009 | 129 | 2009 |
| Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise MD Powell, TN Vijaykumar Low Power Electronics and Design, 2003. ISLPED'03. Proceedings of the 2003 …, 2003 | 79 | 2003 |
| Exploiting resonant behavior to reduce inductive noise MD Powell, TN Vijaykumar ACM SIGARCH Computer Architecture News 32 (2), 288, 2004 | 69 | 2004 |
| Pipeline damping: a microarchitectural technique to reduce inductive noise in supply voltage MD Powell, TN Vijaykumar ACM SIGARCH Computer Architecture News 31 (2), 72-83, 2003 | 69 | 2003 |
| Achieving uniform performance and maximizing throughput in the presence of heterogeneity KK Rangan, MD Powell, GY Wei, D Brooks 2011 IEEE 17th International Symposium on High Performance Computer …, 2011 | 43 | 2011 |
| Balancing resource utilization to mitigate power density in processor pipelines MD Powell, E Schuchman, TN Vijaykumar 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05 …, 2005 | 25 | 2005 |
| Dynamically resizable instruction cache: An energy-efficient and high-performance deep-submicron instruction cache SH Yang, M Powell, B Falsafi, K Roy, TN Vijaykumar ECE Technical Reports, 22, 2000 | 17 | 2000 |
| Exploiting process variation in a multicore processor A Biswas, MD Powell US Patent App. 13/830,157, 2013 | 15 | 2013 |
| General purpose hardware to replace faulty core components that may also provide additional processor functionality SE Raasch, MD Powell, SS Mukherjee, A Biswas US Patent 8,914,672, 2014 | 14 | 2014 |
| An energy-efficient high performance deep submicron instruction cache SH Yang, M Powell, B Falsafi, K Roy, TN Vijaykumar IEEE Transactions on VLSI, Special Issue on Low Power Electronics and Design 1, 2001 | 9* | 2001 |
