Bijan Alizadeh
Cited by
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A resource-limited hardware accelerator for convolutional neural networks in embedded vision applications
S Moini, B Alizadeh, M Emad, R Ebrahimpour
IEEE Transactions on Circuits and Systems II: Express Briefs 64 (10), 1217-1221, 2017
Groebner basis based formal verification of large arithmetic circuits using gaussian elimination and cone-based polynomial extraction
F Farahmandi, B Alizadeh
Microprocessors and Microsystems 39 (2), 83-96, 2015
A formal approach for debugging arithmetic circuits
O Sarbishei, M Tabandeh, B Alizadeh, M Fujita
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009
Modular datapath optimization and verification based on modular-HED
B Alizadeh, M Fujita
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
Dynamic flip-flop conversion: A time-borrowing method for performance improvement of low-power digital circuits prone to variations
M Nejat, B Alizadeh, A Afzali-Kusha
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (11 …, 2014
Polynomial datapath optimization using partitioning and compensation heuristics
O Sarbishei, B Alizadeh, M Fujita
2009 46th ACM/IEEE Design Automation Conference, 931-936, 2009
LTED: a canonical and compact hybrid word-Boolean representation as a formal model for hardware/software co-designs
B Alizadeh, M Fujita
International Workshop on Constraints in Formal Verification (CFV07), 15-29, 2007
FPGA-based implementation of a real-time object recognition system using convolutional neural network
AA Gilan, M Emad, B Alizadeh
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (4), 755-759, 2019
Modular-HED: A canonical decision diagram for modular equivalence verification of polynomial functions
B Alizadeh, M Fujita
fifth Workshop on Constraints in Formal Verification (CFV), 22-40, 2008
Using integer equations for high level formal verification property checking
B Alizadeh, MR Kakoee
Fourth International Symposium on Quality Electronic Design, 2003 …, 2003
PMTP: A MAX-SAT-based approach to detect hardware trojan using propagation of maximum transition probability
A Shabani, B Alizadeh
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
A scalable formal debugging approach with auto-correction capability based on static slicing and dynamic ranking for RTL datapath designs
B Alizadeh, P Behnam, S Sadeghi-Kohan
IEEE Transactions on Computers 64 (6), 1564-1578, 2014
Optimal operation of a virtual power plant with risk management
H Taheri, A Rahimi-Kian, H Ghasemi, B Alizadeh
2012 IEEE PES Innovative Smart Grid Technologies (ISGT), 1-7, 2012
FPGA-based implementation of a novel method for estimating the Brillouin frequency shift in BOTDA and BOTDR sensors
M Abbasnejad, B Alizadeh
IEEE Sensors Journal 18 (5), 2015-2022, 2017
Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs
B Alizadeh, P Behnam
Microprocessors and Microsystems 37 (8), 1108-1121, 2013
Guided gate-level ATPG for sequential circuits using a high-level test generation approach
B Alizadeh, M Fujita
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 425-430, 2010
In-circuit mutation-based automatic correction of certain design errors using SAT mechanisms
P Behnam, B Alizadeh
2015 IEEE 24th Asian Test Symposium (ATS), 199-204, 2015
A new approach for automatic test pattern generation in register transfer level circuits
M Mirzaei, M Tabandeh, B Alizadeh, Z Navabi
IEEE Design & Test 30 (4), 49-59, 2013
Pipelined microprocessors optimization and debugging
B Alizadeh, AM Gharehbaghi, M Fujita
International Symposium on Applied Reconfigurable Computing, 435-444, 2010
Arithmetic circuits verification without looking for internal equivalences
O Sarbishei, B Alizadeh, M Fujita
2008 6th ACM/IEEE International Conference on Formal Methods and Models for …, 2008
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