(Cody) Hao Yu
(Cody) Hao Yu
Applied Scientist at Amazon AI, AWS, PhD of UCLA
Verified email at amazon.com - Homepage
TitleCited byYear
Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs
X Wei, CH Yu, P Zhang, Y Chen, Y Wang, H Hu, Y Liang, J Cong
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
1162017
Programming and runtime support to blaze FPGA accelerator deployment at datacenter scale
M Huang, D Wu, CH Yu, Z Fang, M Interlandi, T Condie, J Cong
Proceedings of the Seventh ACM Symposium on Cloud Computing, 456-469, 2016
502016
On the preconditioner of conjugate gradient method: a power grid simulation perspective
CH Chou, NY Tsai, H Yu, CR Lee, Y Shi, SC Chang
Proceedings of the International Conference on Computer-Aided Design, 494-497, 2010
342010
The SMEM Seeding Acceleration for DNA Sequence Alignment
MCF Chang, YT Chen, J Cong, PT Huang, CL Kuo, CH Yu
The 24th IEEE International Symposium on Field-Programmable Custom Computing …, 2016
302016
Bandwidth Optimization Through On-Chip Memory Restructuring for HLS
J Cong, P Wei, CH Yu, P Zhou
212017
Useful-skew clock optimization for multi-power mode designs
HM Chou, H Yu, SC Chang
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 647-650, 2011
192011
Heterogeneous datacenters: Options and opportunities
J Cong, M Huang, D Wu, CH Yu
Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016
162016
Thermal-aware on-line scheduler for 3-D many-core processor throughput optimization
CH Yu, CL Lung, YL Ho, RS Hsu, DM Kwai, SC Chang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
142014
TGPA: tile-grained pipeline architecture for low latency CNN inference
X Wei, Y Liang, X Li, CH Yu, P Zhang, J Cong
Proceedings of the International Conference on Computer-Aided Design, 1-8, 2018
112018
Automated accelerator generation and optimization with composable, parallel and pipeline architecture
J Cong, P Wei, CH Yu, P Zhang
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 1-6, 2018
112018
S2FA: an accelerator automation framework for heterogeneous computing in datacenters
CH Yu, P Wei, M Grossman, P Zhang, V Sarker, J Cong
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 1-6, 2018
62018
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing
YH Lai, Y Chi, Y Hu, J Wang, CH Yu, Y Zhou, J Cong, Z Zhang
Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019
52019
Latte: Locality Aware Transformation for High-Level Synthesis
J Cong, P Wei, CH Yu, P Zhou
52018
On the futility of thermal through-silicon-vias
CH Chou, NY Tsai, H Yu, Y Shi, JH Chien, SC Chang
2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT), 1-6, 2013
52013
Best-effort FPGA programming: a few steps can go a long way
J Cong, Z Fang, Y Hao, P Wei, CH Yu, C Zhang, P Zhou
arXiv preprint arXiv:1807.01340, 2018
42018
From {JVM} to {FPGA}: Bridging Abstraction Hierarchy via Optimized Deep Pipelining
J Cong, P Wei, CH Yu
10th {USENIX} Workshop on Hot Topics in Cloud Computing (HotCloud 18), 2018
42018
Impact of loop transformations on software reliability
J Cong, CH Yu
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 278-285, 2015
42015
Thermal stress aware design for stacking IC with through glass via
JH Chien, H Yu, CL Lung, HC Chang, NY Tsai, YF Chou, PH Chen, ...
2012 7th International Microsystems, Packaging, Assembly and Circuits …, 2012
32012
Overcoming data transfer bottlenecks in dnn accelerators via layer-conscious memory managment
X Wei, Y Liang, P Zhang, CH Yu, J Cong
Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019
12019
Raising an Abstraction Level of Compilation and Optimization for Customized Computing
H Yu, J Cong
UCLA, 2019
2019
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Articles 1–20