Seth H Pugsley
Seth H Pugsley
Research Scientist, Intel Labs
Verified email at cs.utah.edu
Title
Cited by
Cited by
Year
NDC: Analyzing the impact of 3D-stacked memory+ logic devices on MapReduce workloads
SH Pugsley, J Jestes, H Zhang, R Balasubramonian, V Srinivasan, ...
2014 IEEE International Symposium on Performance Analysis of Systems and …, 2014
2492014
Usimm: the utah simulated memory module
N Chatterjee, R Balasubramonian, M Shevgoor, S Pugsley, A Udipi, ...
University of Utah, Tech. Rep, 1-24, 2012
1702012
Efficiently prefetching complex address patterns
M Shevgoor, S Koladiya, R Balasubramonian, C Wilkerson, SH Pugsley, ...
2015 48th Annual IEEE/ACM International Symposium on Microarchitecture …, 2015
1132015
Sandbox prefetching: Safe run-time evaluation of aggressive prefetchers
SH Pugsley, Z Chishti, C Wilkerson, P Chuang, RL Scott, A Jaleel, SL Lu, ...
2014 IEEE 20th International Symposium on High Performance Computer …, 2014
972014
SWEL: Hardware cache coherence protocols to map shared data onto shared caches
SH Pugsley, JB Spjut, DW Nellans, R Balasubramonian
Proceedings of the 19th international conference on Parallel architectures …, 2010
832010
Path confidence based lookahead prefetching
J Kim, SH Pugsley, PV Gratz, ALN Reddy, C Wilkerson, Z Chishti
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
802016
Comparing implementations of near-data computing with in-memory mapreduce workloads
SH Pugsley, J Jestes, R Balasubramonian, V Srinivasan, ...
IEEE Micro 34 (4), 44-52, 2014
722014
Scalable and reliable communication for hardware transactional memory
SH Pugsley, M Awasthi, N Madan, N Muralimanohar, R Balasubramonian
2008 International Conference on Parallel Architectures and Compilation …, 2008
532008
Kill the program counter: Reconstructing program behavior in the processor cache hierarchy
J Kim, E Teran, PV Gratz, DA Jiménez, SH Pugsley, C Wilkerson
ACM SIGPLAN Notices 52 (4), 737-749, 2017
352017
Perceptron-based prefetch filtering
E Bhatia, G Chacon, S Pugsley, E Teran, PV Gratz, DA Jiménez
2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture …, 2019
312019
Memory bandwidth reservation in the cloud to avoid information leakage in the memory controller
A Gundu, G Sreekumar, A Shafiee, S Pugsley, H Jain, ...
Proceedings of the Third Workshop on Hardware and Architectural Support for …, 2014
212014
Usimm: the utah simulated memory module a simulation infrastructure for the jwac memory scheduling championship
N Chatterjee, R Balasubramonian, M Shevgoor, SH Pugsley, AN Udipi, ...
192012
Fixed-function hardware sorting accelerators for near data mapreduce execution
SH Pugsley, A Deb, R Balasubramonian, F Li
2015 33rd IEEE International Conference on Computer Design (ICCD), 439-442, 2015
132015
Optimizing a multi-core processor for message-passing workloads
N Chatterjee, SH Pugsley, J Spjut, R Balasubramonian
Proceedings of the Workshop on Unique Chips and Systems (UCAS-5), 2009
112009
Instruction and logic for run-time evaluation of multiple prefetchers
ZA Chishti, CB Wilkerson, S Pugsley, PF Chuang, RL Scott, A Jaleel, ...
US Patent 9,378,021, 2016
102016
Opportunities for near data computing in MapReduce workloads
SH Pugsley
The University of Utah, 2015
42015
System and method for cache replacement using conservative set dueling
SH Pugsley, CB Wilkerson, R Gramunt, JC Hall, P Jain
US Patent 10,007,620, 2018
32018
Multiple subarray memory access
N Muralimanohar, NP Jouppi, R Balasubramonian, S Pugsley, ...
US Patent App. 13/715,163, 2014
32014
Neuromorphic accelerator multitasking
S Pugsley, B Akin
US Patent App. 15/937,486, 2019
22019
Spiking neural network accelerator using external memory
B Akin, S Pugsley
US Patent App. 15/853,282, 2019
22019
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Articles 1–20