| Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction A Saifhashemi, H Pedram Proceedings of the 40th annual Design Automation Conference, 330-333, 2003 | 62 | 2003 |
| Power aware asynchronous circuits K Shiring, PA Beerel, A Lines, A Saifhashemi US Patent 8,086,975, 2011 | 30 | 2011 |
| Power aware asynchronous circuits K Shiring, PA Beerel, A Lines, A Saifhashemi US Patent 8,086,975, 2011 | 30 | 2011 |
| Power aware asynchronous circuits K Shiring, PA Beerel, A Lines, A Saifhashemi US Patent 8,086,975, 2011 | 30 | 2011 |
| High level modeling of channel-based asynchronous circuits using verilog A Saifhashemi, PA Beerel Communicating Process Architectures 2005, 275-288, 2005 | 17 | 2005 |
| SystemVerilogCSP: Modeling digital asynchronous circuits using SystemVerilog interfaces A Saifhashemi, PA Beerel Communicating Process Architectures 2011, 287-302, 2011 | 16 | 2011 |
| Performance and area optimization of a bundled-data intel processor through resynthesis A Saifhashemi, D Hand, PA Beerel, W Koven, H Wang 2014 20th IEEE International Symposium on Asynchronous Circuits and Systems …, 2014 | 13 | 2014 |
| MILO: Personal robot platform B Salemi, J Reis, A Saifhashemi, F Nikgohar 2005 IEEE/RSJ International Conference on Intelligent Robots and Systems …, 2005 | 12 | 2005 |
| Power optimization of asynchronous pipelines using conditioning and reconditioning based on a three-valued logic model A Saifhashemi University of Southern California, 2012 | 7 | 2012 |
| Notes On Pulse Signaling. JC Ebergen, S Furber, A Saifhashemi, N Nissar, A Chow ASYNC, 15-24, 2007 | 7 | 2007 |
| Logical equivalence checking of asynchronous circuits using commercial tools A Saifhashemi, HH Huang, P Bhalerao, PA Beerel 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 6 | 2015 |
| Observability conditions and automatic operand-isolation in high-throughput asynchronous pipelines A Saifhashemi, PA Beerel Integrated Circuit and System Design. Power and Timing Modeling …, 2013 | 6 | 2013 |
| PERSIA: An Asynchronous Synthesis Tool Based on Alain Martin's Method A Seifhashemi, M Naderi, K Saleh, M Salehi, H Pedram CAD Tutorial, Proc. of 9th IEEE International Symposium on Asynchronous …, 2003 | 6 | 2003 |
| Reconditioning: Automatic power optimization of QDI circuits A Saifhashemi, HH Huang, PA Beerel 2014 20th IEEE International Symposium on Asynchronous Circuits and Systems …, 2014 | 4 | 2014 |
| Verilog HDL, a Replacement for CSP A Seifhashemi, H Pedram 3rd Asynchronous Circuit Design Workshop-ACiD-WG, Heraklion, Greece, 2003 | 4 | 2003 |
| High level modeling of channel-based asynchronous circuits using verilog J Broenink, H Roebbers, J Sunter, P Welch, D Wood Communicating Process Architectures, 275, 2005 | 2 | 2005 |
| Reconditioning: a framework for automatic power optimization of QDI circuits A Saifhashemi, HH Huang, PA Beerel IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 1 | 2016 |
| Using standard HDLs and CAD tools for the design and simulation of asynchronous circuit A Saifhashemi, M Naderi, H Pedram, A Farhoodfar CSI J Comput Sci Eng 1 (4), 1-10, 2003 | 1 | 2003 |
| Notes On Pulse Signaling A Chow, N Nissar, A Saifhashemi, S Furber, J Ebergen 13th IEEE International Symposium on Asynchronous Circuits and Systems …, 2007 | | 2007 |
| Verilog HDL, Powered by PLI: for Describing and Modeling Asynchronous Circuits at All Levels of Abstraction A Saifhashemi | | 2003 |
