| Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks YH Chen, T Krishna, JS Emer, V Sze IEEE journal of solid-state circuits 52 (1), 127-138, 2016 | 2450 | 2016 |
| Efficient processing of deep neural networks: A tutorial and survey V Sze, YH Chen, TJ Yang, JS Emer Proceedings of the IEEE 105 (12), 2295-2329, 2017 | 2421 | 2017 |
| Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks YH Chen, J Emer, V Sze ACM SIGARCH computer architecture news 44 (3), 367-379, 2016 | 1286 | 2016 |
| A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor SS Mukherjee, C Weaver, J Emer, SK Reinhardt, T Austin Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003 | 1195 | 2003 |
| Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor DM Tullsen, SJ Eggers, JS Emer, HM Levy, JL Lo, RL Stamm Proceedings of the 23rd annual international symposium on Computer …, 1996 | 1191 | 1996 |
| Adaptive insertion policies for high performance caching MK Qureshi, A Jaleel, YN Patt, SC Steely, J Emer ACM SIGARCH Computer Architecture News 35 (2), 381-391, 2007 | 890 | 2007 |
| SCNN: An accelerator for compressed-sparse convolutional neural networks A Parashar, M Rhu, A Mukkara, A Puglielli, R Venkatesan, B Khailany, ... ACM SIGARCH computer architecture news 45 (2), 27-40, 2017 | 885 | 2017 |
| High performance cache replacement using re-reference interval prediction (RRIP) A Jaleel, KB Theobald, SC Steely Jr, J Emer ACM SIGARCH Computer Architecture News 38 (3), 60-71, 2010 | 836 | 2010 |
| Simultaneous multithreading: A platform for next-generation processors SJ Eggers, JS Emer, HM Levy, JL Lo, RL Stamm, DM Tullsen IEEE micro 17 (5), 12-19, 1997 | 695 | 1997 |
| The soft error problem: An architectural perspective SS Mukherjee, J Emer, SK Reinhardt 11th International Symposium on High-Performance Computer Architecture, 243-247, 2005 | 553 | 2005 |
| Memory dependence prediction using store sets GZ Chrysos, JS Emer ACM SIGARCH Computer Architecture News 26 (3), 142-153, 1998 | 454 | 1998 |
| Eyeriss v2: A flexible accelerator for emerging deep neural networks on mobile devices YH Chen, TJ Yang, J Emer, V Sze IEEE Journal on Emerging and Selected Topics in Circuits and Systems 9 (2 …, 2019 | 444 | 2019 |
| Scheduling heterogeneous multi-cores through performance impact estimation (PIE) K Van Craeynest, A Jaleel, L Eeckhout, P Narvaez, J Emer 2012 39th annual international symposium on computer architecture (ISCA …, 2012 | 412 | 2012 |
| Adaptive insertion policies for managing shared caches A Jaleel, W Hasenplaugh, M Qureshi, J Sebot, S Steely Jr, J Emer Proceedings of the 17th international conference on Parallel architectures …, 2008 | 403 | 2008 |
| Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading JL Lo, JS Emer, HM Levy, RL Stamm, DM Tullsen, SJ Eggers ACM Transactions on Computer Systems (TOCS) 15 (3), 322-354, 1997 | 373 | 1997 |
| Techniques to reduce the soft error rate of a high-performance microprocessor C Weaver, J Emer, SS Mukherjee, SK Reinhardt ACM SIGARCH Computer Architecture News 32 (2), 264, 2004 | 370 | 2004 |
| Asim: A performance model framework J Emer, P Ahuja, E Borch, A Klauser, CK Luk, S Manne, SS Mukherjee, ... Computer 35 (2), 68-76, 2002 | 312 | 2002 |
| Predictive sequential associative cache B Calder, D Grunwald, J Emer Proceedings. Second International Symposium on High-Performance Computer …, 1996 | 291 | 1996 |
| Computing architectural vulnerability factors for address-based structures A Biswas, P Racunas, R Cheveresan, J Emer, SS Mukherjee, R Rangan 32nd International Symposium on Computer Architecture (ISCA'05), 532-543, 2005 | 287 | 2005 |
| SHiP: Signature-based hit predictor for high performance caching CJ Wu, A Jaleel, W Hasenplaugh, M Martonosi, SC Steely Jr, J Emer Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011 | 283 | 2011 |
Vivienne SzeAssociate Professor, EECS at MITVerified email at mit.edu
