Joel Emer - Google Scholar Citations

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	All	Since 2015
Citations	16018	7691
h-index	56	39
i10-index	117	82

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Co-authors

Aamer JaleelArchitecture Research Group (ARG), Nvidia ResearchVerified email at nvidia.com
Steven K. ReinhardtMicrosoftVerified email at microsoft.com
Vivienne SzeAssociate Professor, EECS at MITVerified email at mit.edu
Yu-Hsin ChenResearch Scientist, FacebookVerified email at fb.com
Angshuman ParasharSr. Research Scientist, NVIDIAVerified email at nvidia.com
Steve KecklerVice President of Architecture Research, NVIDIAVerified email at cs.utexas.edu
Dean TullsenProfessor of Computer Science and Engineering, UC San DiegoVerified email at eng.ucsd.edu
William HasenplaughD. E. Shaw ResearchVerified email at mit.edu
Susan J EggersProfessor of Computer Science, University of WashingtonVerified email at cs.washington.edu
Henry M. LevyDirector and Wissner-Slivka Chair, Paul G. Allen School of Computer Science & EngineeringVerified email at cs.washington.edu
Kermin Elliott FlemingIntel CorporationVerified email at intel.com
Rangharajan VenkatesanNVIDIA ResearchVerified email at nvidia.com
Tien-Ju YangMassachusetts Institute of TechnologyVerified email at mit.edu
William DallyBell Professor of Engineering, Stanford UniversityVerified email at stanford.edu
Todd AustinProfessor of Computer Science and Electrical Engineering, University of MichiganVerified email at umich.edu
Toni JuanAssociate Professort, Computer Architecture Department, UPCVerified email at ac.upc.edu
Tushar KrishnaAssistant Professor, Georgia TechVerified email at ece.gatech.edu
Moinuddin QureshiProfessor, Georgia Institute of TechnologyVerified email at gatech.edu
Neal CragoSenior Research Scientist, Nvidia ResearchVerified email at nvidia.com
Craig ZillesAssociate Professor of Computer Science, University of Illinois at Urbana-ChampaignVerified email at illinois.edu

Joel Emer

Sr. Distinguished Research Scientist, Nvidia - Professor of the Practice, MIT

Verified email at csail.mit.edu

Computer Architecture


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Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks YH Chen, T Krishna, JS Emer, V Sze IEEE journal of solid-state circuits 52 (1), 127-138, 2016	1187	2016
Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor DM Tullsen, SJ Eggers, JS Emer, HM Levy, JL Lo, RL Stamm Proceedings of the 23rd annual international symposium on Computer …, 1996	1100	1996
A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor SS Mukherjee, C Weaver, J Emer, SK Reinhardt, T Austin Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003	1025	2003
Efficient processing of deep neural networks: A tutorial and survey V Sze, YH Chen, TJ Yang, JS Emer Proceedings of the IEEE 105 (12), 2295-2329, 2017	827	2017
Adaptive insertion policies for high performance caching MK Qureshi, A Jaleel, YN Patt, SC Steely, J Emer ACM SIGARCH Computer Architecture News 35 (2), 381-391, 2007	718	2007
High performance cache replacement using re-reference interval prediction (RRIP) A Jaleel, KB Theobald, SC Steely Jr, J Emer ACM SIGARCH Computer Architecture News 38 (3), 60-71, 2010	632	2010
Simultaneous multithreading: A platform for next-generation processors SJ Eggers, JS Emer, HM Levy, JL Lo, RL Stamm, DM Tullsen IEEE micro 17 (5), 12-19, 1997	629	1997
Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks YH Chen, J Emer, V Sze ACM SIGARCH Computer Architecture News 44 (3), 367-379, 2016	608	2016
The soft error problem: An architectural perspective SS Mukherjee, J Emer, SK Reinhardt 11th International Symposium on High-Performance Computer Architecture, 243-247, 2005	470	2005
Memory dependence prediction using store sets GZ Chrysos, JS Emer ACM SIGARCH Computer Architecture News 26 (3), 142-153, 1998	404	1998
Adaptive insertion policies for managing shared caches A Jaleel, W Hasenplaugh, M Qureshi, J Sebot, S Steely Jr, J Emer Proceedings of the 17th international conference on Parallel architectures …, 2008	357	2008
Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading JL Lo, JS Emer, HM Levy, RL Stamm, DM Tullsen, SJ Eggers ACM Transactions on Computer Systems (TOCS) 15 (3), 322-354, 1997	353	1997
Scnn: An accelerator for compressed-sparse convolutional neural networks A Parashar, M Rhu, A Mukkara, A Puglielli, R Venkatesan, B Khailany, ... ACM SIGARCH Computer Architecture News 45 (2), 27-40, 2017	350	2017
Scheduling heterogeneous multi-cores through performance impact estimation (PIE) K Van Craeynest, A Jaleel, L Eeckhout, P Narvaez, J Emer 2012 39th Annual International Symposium on Computer Architecture (ISCA …, 2012	343	2012
Techniques to reduce the soft error rate of a high-performance microprocessor C Weaver, J Emer, SS Mukherjee, SK Reinhardt ACM SIGARCH Computer Architecture News 32 (2), 264, 2004	336	2004
Asim: A performance model framework J Emer, P Ahuja, E Borch, A Klauser, CK Luk, S Manne, SS Mukherjee, ... Computer 35 (2), 68-76, 2002	282	2002
Predictive sequential associative cache B Calder, D Grunwald, J Emer Proceedings. Second International Symposium on High-Performance Computer …, 1996	277	1996
Computing architectural vulnerability factors for address-based structures A Biswas, P Racunas, R Cheveresan, J Emer, SS Mukherjee, R Rangan 32nd International Symposium on Computer Architecture (ISCA'05), 532-543, 2005	251	2005
SHiP: Signature-based hit predictor for high performance caching CJ Wu, A Jaleel, W Hasenplaugh, M Martonosi, SC Steely Jr, J Emer Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011	218	2011
Loose loops sink chips E Borch, E Tune, S Manne, J Emer Proceedings Eighth International Symposium on High Performance Computer …, 2002	201	2002

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