| SRAM cells with two P-well structure K Osada, M Minami, S Ikeda, K Ishibashi US Patent 6,677,649, 2004 | 368 | 2004 |
| Semiconductor memory device K Nii, S Obayashi, H Makino, K Ishibashi, H Shinohara US Patent 7,502,275, 2009 | 232 | 2009 |
| SRAM having load transistor formed above driver transistor S Ikeda, S Meguro, S Hashiba, I Kuramoto, A Koike, K Sasaki, K Ishibashi, ... US Patent 5,834,851, 1998 | 215 | 1998 |
| A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits S Ohbayashi, M Yabuuchi, K Nii, Y Tsukamoto, S Imaoka, Y Oda, ... IEEE journal of solid-state circuits 42 (4), 820-829, 2007 | 195 | 2007 |
| Semiconductor memory device with memory cells operated by boosted voltage M Yamaoka, K Osada, K Ishibashi US Patent 6,795,332, 2004 | 168 | 2004 |
| 16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors K Osada, Y Saitoh, E Ibe, K Ishibashi IEEE Journal of Solid-State Circuits 38 (11), 1952-1957, 2003 | 149 | 2003 |
| An 18-/spl mu/A standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode H Mizuno, K Ishibashi, T Shimura, T Hattori, S Narita, K Shiozawa, S Ikeda, ... IEEE Journal of Solid-State Circuits 34 (11), 1492-1500, 1999 | 126 | 1999 |
| 0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme M Yamaoka, K Osada, K Ishibashi IEEE Journal of Solid-State Circuits 39 (6), 934-940, 2004 | 120 | 2004 |
| Universal-V/sub dd/0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell K Osada, JL Shin, M Khan, Y Liou, K Wang, K Shoji, K Kuroda, S Ikeda, ... IEEE Journal of Solid-State Circuits 36 (11), 1738-1744, 2001 | 117 | 2001 |
| Semiconductor device with low power consumption memory circuit M Yamaoka, K Ishibashi, S Matsui, K Osada US Patent 6,657,911, 2003 | 114 | 2003 |
| A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias M Miyazaki, G Ono, K Ishibashi IEEE Journal of Solid-State Circuits 37 (2), 210-217, 2002 | 113 | 2002 |
| A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier K Sasaki, K Ishibashi, K Ueda, K Komiyaji, T Yamanaka, N Hashimoto, ... IEEE Journal of Solid-State Circuits 27 (11), 1511-1518, 1992 | 104 | 1992 |
| A 9-ns 1-Mbit CMOS SRAM K Sasaki, K Ishibashi, T Yamanaka, N Hashimoto, T Nishida, ... IEEE journal of solid-state circuits 24 (5), 1219-1225, 1989 | 104 | 1989 |
| Semiconductor integrated circuit device K Ishibashi, K Osada US Patent 6,424,015, 2002 | 95 | 2002 |
| A 65 nm embedded sram with wafer level burn-in mode, leak-bit redundancy and cu e-trim fuse for known good die S Ohbayashi, M Yabuuchi, K Kono, Y Oda, S Imaoka, K Usui, T Yonezu, ... IEEE journal of solid-state circuits 43 (1), 96-108, 2008 | 90 | 2008 |
| Advanced TFT SRAM cell technology using a phase-shift lithography T Yamanaka, T Hashimoto, N Hasegawa, T Tanaka, N Hashimoto, ... IEEE transactions on electron devices 42 (7), 1305-1313, 1995 | 90 | 1995 |
| A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias M Miyazaki, G Ono, T Hattori, K Shiozawa, K Uchiyama, K Ishibashi 2000 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2000 | 89 | 2000 |
| A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers K Ishibashi, K Takasugi, K Komiyaji, H Toyoshima, T Yamanaka, ... IEICE transactions on electronics 78 (6), 728-734, 1995 | 89 | 1995 |
| Semiconductor integrated circuit device including a speed monitor circuit and a substrate bias controller responsive to the speed-monitor circuit M Miyazaki, K Ishibashi, G Ono US Patent 6,466,077, 2002 | 88 | 2002 |
| A 5.9 mu m/sup 2/super low power SRAM cell using a new phase-shift lithography T Yamanaka, N Hasegawa, T Tanaka, K Ishibashi, T Hashimoto, ... International Technical Digest on Electron Devices, 477-480, 1990 | 83 | 1990 |
