| Communication node architecture in a globally asynchronous network on chip system E Beigne, P Vivet, M Renaudin, J Quartana US Patent 7,940,666, 2011 | 30 | 2011 |
| GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips J Quartana, S Renane, A Baixas, L Fesquet, M Renaudin International Conference on Field Programmable Logic and Applications, 2005 …, 2005 | 24 | 2005 |
| High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. JB Rigaud, L Fesquet, M Renaudin, J Quartana date 1090, 2002, 2002 | 16 | 2002 |
| Modeling and design of asynchronous priority arbiters for on-chip communication systems JB Rigaud, J Quartana, L Fesquet, M Renaudin SOC Design Methodologies: IFIP TC10/WG10. 5 Eleventh International …, 2002 | 13 | 2002 |
| Asynchronous Systems on Programmable Logic. L Fesquet, J Quartana, M Renaudin ReCoSoC, 105-112, 2005 | 6 | 2005 |
| Conception de réseaux de communication sur puce asynchrones: application aux architectures GALS J Quartana Institut National Polytechnique de Grenoble-INPG, 2004 | 6 | 2004 |
| Modular asynchronous Network-on-Chip: application to GALS systems rapid prototyping J Quartana, L Fesquet, M Renaudin Vlsi-Soc: From Systems To Silicon: Proceedings of IFIP TC 10, WG 10.5 …, 2007 | 4 | 2007 |
| Integrated Evaluation Platform for Secured Devices P Manet, JB Rigaud, J Francq, M Jeambrun, B Robisson, J Quartana, ... Reconfigurable Communication-centric Systems-on-Chip, p214-220, 2006 | 2 | 2006 |
| Design of Asynchronous Network on Chip: application to GALS systems J Quartana Thèse de doctorat, Institut National Polytechnique de Grenoble (INPG), 2004 | 2 | 2004 |
| Présentation du GIP-CNFM-CIME Nanotech A Aitoumeri Abdelhamid Aitoumeri, 2023 | | 2023 |
| Étude de la réception d'une bibliothèque interactive auprès d'un public d'enfants J Quartana, S Odena Bulletin des bibliothèques de France, 24-30, 2011 | | 2011 |
| TIC et rapport à la lecture S Odena, J Quartana | | 2011 |
| VLSI-SOC: From Systems to Chips,(selected contributions from VLSI-SoC 2005) J Quartana, L Fesquet, M Renaudin VLSI-SOC: From Systems to Chips,(selected contributions from VLSI-SoC 2005 …, 2007 | | 2007 |
| Communication node architecture in a globally asynchronous network on chip system J Quartana, M Renaudin, P Vivet, E Beigne | | 2006 |
| La conception de circuits asynchrones et la faible consommation M Renaudin, L Fesquet, G Sicard, K Slimani, J Fragoso, E Allier, ... | | 2003 |
