Analytical modeling of a high-K underlap dielectric-and charge-modulated silicon-on-nothing FET-based biosensor KN Singh, PK Dutta Journal of Computational Electronics 19 (3), 1126-1135, 2020 | 14 | 2020 |
Analytical modeling of linearly graded alloy material gate recessed ultra thin body source/drain SON MOSFET PK Dutta, B Manna, SK Sarkar Superlattices and Microstructures 77, 64-75, 2015 | 13 | 2015 |
Design of a DPSK Modem Using CORDIC Algorithm and Its FPGA Implementation J Bag, S Roy, PK Dutta, SK Sarkar IETE Journal of Research 60 (5), 355-363, 2014 | 9 | 2014 |
An improved charge‐sharing elimination pseudo‐domino logic SR Ghimiray, P Meher, PK Dutta International Journal of Circuit Theory and Applications 48 (8), 1346-1362, 2020 | 8 | 2020 |
Ultralow power, noise immune stacked‐double stage clocked‐inverter domino technique for ultradeep submicron technology SR Ghimiray, P Meher, PK Dutta International Journal of Circuit Theory and Applications 46 (11), 1953-1967, 2018 | 8 | 2018 |
Analytical modeling of underlap graded channel field effect transistor as a label-free biosensor KN Singh, PK Dutta Superlattices and Microstructures 155, 106897, 2021 | 7 | 2021 |
Threshold voltage roll-off and DIBL model for DMDG SON MOSFET: a quantum study S Shee, G Bhattacharyya, PK Dutta, SK Sarkar Proceedings of the 2014 IEEE Students' Technology Symposium, 381-385, 2014 | 5 | 2014 |
Review and analysis of charge-pump phase-locked loop M Gogoi, PK Dutta Electronic Systems and Intelligent Computing: Proceedings of ESIC 2020, 565-574, 2020 | 4 | 2020 |
Implementation of Universal Gates (NAND) Based on Nano-Magnetic Logic Using Multiferroics A Sarkar, PK Dutta, A Ghosh, S Ray, SK Sarkar Quantum Matter 5 (4), 505-509, 2016 | 4 | 2016 |
Design and implementation of 4-bit ripple carry adder using SETMOS architecture D Rajkumar, PK Dutta, SK Sarkar 2016 IEEE International Conference on Recent Trends in Electronics …, 2016 | 4 | 2016 |
Analysis and simulation of dual metal double gate son mosfet using hafnium dioxide for better performance PK Dutta, N Bagga, K Naskar, SK Sarkar IET Digital Library, 2015 | 4 | 2015 |
Quantum confinement effects in the subthreshold characteristics of short-channel DMDG MOSFET S Shee, G Bhattacharyya, PK Dutta, SK Sarkar Proceedings of The 2014 International Conference on Control, Instrumentation …, 2014 | 4 | 2014 |
Quantum analytical modeling and simulation of CNT on insulator (COI) and CNT on nothing (CON) FET: a comparative analysis S Mukherjee, D Bandyopadhyay, PK Dutta, SK Sarkar Journal of Theoretical and Applied Physics 10, 91-97, 2016 | 3 | 2016 |
Analytical investigation of a split double gate graded channel field effect transistor for biosensing applications KN Singh, PK Dutta Silicon 14 (17), 11303-11313, 2022 | 2 | 2022 |
Analytical Design of FET-Based Biosensors KN Singh, PK Dutta Advanced VLSI Design and Testability Issues, 147-167, 2020 | 2 | 2020 |
Comparative Analysis of Underlapped Silicon on Insulator and Underlapped Silicon on Nothing Dielectric and Charge Modulated FET based Biosensors KN Singh, PK Dutta 2019 Devices for Integrated Circuit (DevIC), 231-235, 2019 | 2 | 2019 |
Error probability independent delay analysis of single electronics circuits A Jain, A Ghosh, PK Dutta, NB Singh, SK Sarkar International Journal of Circuit Theory and Applications 46 (2), 290-298, 2018 | 2 | 2018 |
Energy efficient, noise immune 4× 4 Vedic multiplier using semi-domino logic style SR Ghimiray, P Meher, PK Dutta Region 10 Conference, TENCON 2017-2017 IEEE, 1037-1041, 2017 | 2 | 2017 |
A comparative study for disease identification from heart auscultation using FFT, cepstrum and DCT correlation coefficients S Majumder, S Pal, PK Dutta 13th International Conference on Biomedical Engineering: ICBME 2008 3–6 …, 2009 | 2 | 2009 |
DESIGN OF A FOUR STAGES VCO USING A NOVEL DELAY CIRCUIT FOR OPERATION IN DISTRIBUTED BAND FREQUENCIES M Gogoi, PK Dutta Facta Universitatis, Series: Electronics and Energetics 35 (4), 469-482, 2022 | 1 | 2022 |