2-D Analytical Modeling of the Electrical Characteristics of Dual-Material Double-Gate TFETs With a SiO2 /HfO2 Stacked Gate-Oxide Structure S Kumar, E Goel, K Singh, B Singh, PK Singh, K Baral, S Jit
IEEE Transactions on Electron Devices 64 (3), 960-968, 2017
170 2017 A Compact 2-D Analytical Model for Electrical Characteristics of Double-Gate Tunnel Field-Effect Transistors With a SiO2 /High- Stacked Gate-Oxide Structure S Kumar, E Goel, K Singh, B Singh, M Kumar, S Jit
IEEE Transactions on Electron Devices 63 (8), 3291-3299, 2016
142 2016 2-D analytical modeling of threshold voltage for graded-channel dual-material double-gate MOSFETs E Goel, S Kumar, K Singh, B Singh, M Kumar, S Jit
IEEE Transactions on Electron Devices 63 (3), 966-973, 2016
109 2016 Analytical modeling of channel potential and threshold voltage of double-gate junctionless FETs with a vertical Gaussian-like doping profile B Singh, D Gola, K Singh, E Goel, S Kumar, S Jit
IEEE Transactions on Electron Devices 63 (6), 2299-2305, 2016
75 2016 2-D Analytical Drain Current Model of Double-Gate Heterojunction TFETs With a SiO2 /HfO2 Stacked Gate-Oxide Structure S Kumar, K Singh, S Chander, E Goel, PK Singh, K Baral, B Singh, S Jit
IEEE Transactions on Electron Devices 65 (1), 331-338, 2017
69 2017 Temperature analysis of Ge/Si heterojunction SOI-tunnel FET S Chander, SK Sinha, S Kumar, PK Singh, K Baral, K Singh, S Jit
Superlattices and Microstructures 110, 162-170, 2017
58 2017 Dielectric pocket double gate junctionless FET: a new MOS structure with improved subthreshold characteristics for low power VLSI applications B Singh, D Gola, E Goel, S Kumar, K Singh, S Jit
Journal of Computational Electronics 15 (2), 502-507, 2016
41 2016 2-D analytical threshold voltage model for dielectric pocket double-gate junctionless FETs by considering source/drain depletion effect B Singh, D Gola, K Singh, E Goel, S Kumar, S Jit
IEEE Transactions on Electron Devices 64 (3), 901-908, 2017
38 2017 Analytical modeling of subthreshold characteristics of ion-implanted symmetric double gate junctionless field effect transistors B Singh, D Gola, K Singh, E Goel, S Kumar, S Jit
Materials science in semiconductor processing 58, 82-88, 2017
26 2017 Ferro-electric stacked gate oxide heterojunction electro-statically doped source/drain double-gate tunnel field effect transistors: A superior structure B Singh, TN Rai, D Gola, K Singh, E Goel, S Kumar, PK Tiwari, S Jit
Materials Science in Semiconductor Processing 71, 161-165, 2017
20 2017 Analytical modeling of subthreshold current and subthreshold swing of Gaussian-doped strained-Si-on-insulator MOSFETs G Rawat, S Kumar, E Goel, M Kumar, S Dubey, S Jit
Journal of Semiconductors 35 (8), 084001, 2014
18 2014 Two-dimensional model for subthreshold current and subthreshold swing of graded-channel dual-material double-gate (GCDMDG) MOSFETs E Goel, S Kumar, B Singh, K Singh, S Jit
Superlattices and Microstructures 106, 147-155, 2017
15 2017 Analytical threshold voltage modeling of ion-implanted strained-Si double-material double-gate (DMDG) MOSFETs E Goel, B Singh, S Kumar, K Singh, S Jit
Indian Journal of Physics 91, 383-390, 2017
12 2017 Kink effect in TiO2 embedded ZnO quantum dot‐based thin film transistors H Kumar, Y Kumar, K Singh, S Kumar, G Rawat, C Kumar, BN Pal, S Jit
Electronics Letters 53 (4), 262-264, 2017
12 2017 Analytical modeling of potential distribution and threshold voltage of gate underlap DG MOSFETs with a source/drain lateral Gaussian doping profile K Singh, M Kumar, E Goel, B Singh, S Dubey, S Kumar, S Jit
Journal of Electronic Materials 45, 2184-2192, 2016
9 2016 Strain-induced plasma radiation in Terahertz domain in Strained-Si-on-Insulator MOSFETs M Kumar, S Kumar, E Goel, K Singh, B Singh, S Jit
IEEE Transactions on Plasma Science 44 (3), 245-249, 2016
7 2016 Analytical modeling of threshold voltage of ion-implanted Strained-Si-on-Insulator (SSOI) MOSFETs G Rawat, E Goel, S Kumar, M Kumar, S Dubey, S Jit
Journal of Nanoelectronics and Optoelectronics 9 (3), 442-448, 2014
7 2014 Temperature sensitivity analysis of double gate junctionless field effect transistor with vertical Gaussian doping profile B Singh, D Gola, K Singh, E Goel, S Kumar, S Jit
2016 International Conference on Micro-Electronics and Telecommunication …, 2016
5 2016 Two-dimensional analytical model for threshold voltage of graded-channel SOI MOSFETs V Goel, S Sharma, S Kumar, S Jit
2014 IEEE 2nd International Conference on Emerging Electronics (ICEE), 1-4, 2014
4 2014 Subthreshold Current and Swing Modeling of Gate Underlap DG MOSFETs with a Source/Drain Lateral Gaussian Doping Profile K Singh, S Kumar, E Goel, B Singh, M Kumar, S Dubey, S Jit
Journal of Electronic Materials 46, 579-584, 2017
3 2017