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Pai-Yu Chen
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SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations
S Choi, SH Tan, Z Li, Y Kim, C Choi, PY Chen, H Yeon, S Yu, J Kim
Nature materials 17 (4), 335-340, 2018
5882018
Emerging memory technologies: Recent trends and prospects
S Yu, PY Chen
IEEE Solid-State Circuits Magazine 8 (2), 43-56, 2016
5302016
Ferroelectric FET analog synapse for acceleration of deep neural network training
M Jerry, PY Chen, J Zhang, P Sharma, K Ni, S Yu, S Datta
2017 IEEE international electron devices meeting (IEDM), 6.2. 1-6.2. 4, 2017
5082017
NeuroSim: A circuit-level macro model for benchmarking neuro-inspired architectures in online learning
PY Chen, X Peng, S Yu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
4222018
NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures
PY Chen, X Peng, S Yu
2017 IEEE International Electron Devices Meeting (IEDM), 6.1. 1-6.1. 4, 2017
3162017
Compact modeling of RRAM devices and its applications in 1T1R and 1S1R array design
PY Chen, S Yu
IEEE Transactions on Electron Devices 62 (12), 4022-4028, 2015
3142015
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS/W fully parallel product-sum operation for binary DNN edge processors
WS Khwa, JJ Chen, JF Li, X Si, EY Yang, X Sun, R Liu, PY Chen, Q Li, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 496-498, 2018
2462018
Mitigating effects of non-ideal synaptic device characteristics for on-chip learning
PY Chen, B Lin, IT Wang, TH Hou, J Ye, S Vrudhula, J Seo, Y Cao, S Yu
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 194-199, 2015
2432015
Binary neural network with 16 Mb RRAM macro chip for classification and online training
S Yu, Z Li, PY Chen, H Wu, B Gao, D Wang, W Wu, H Qian
2016 IEEE International Electron Devices Meeting (IEDM), 16.2. 1-16.2. 4, 2016
2392016
Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect
S Yu, PY Chen, Y Cao, L Xia, Y Wang, H Wu
2015 IEEE International Electron Devices Meeting (IEDM), 17.3. 1-17.3. 4, 2015
2182015
MNSIM: Simulation platform for memristor-based neuromorphic computing system
L Xia, B Li, T Tang, P Gu, PY Chen, S Yu, Y Cao, Y Wang, Y Xie, H Yang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
1942017
Demonstration of convolution kernel operation on resistive cross-point array
L Gao, PY Chen, S Yu
IEEE Electron Device Letters 37 (7), 870-873, 2016
1482016
NbOx based oscillation neuron for neuromorphic computing
L Gao, PY Chen, S Yu
Applied physics letters 111 (10), 2017
1392017
Device and materials requirements for neuromorphic computing
R Islam, H Li, PY Chen, W Wan, HY Chen, B Gao, H Wu, S Yu, ...
Journal of Physics D: Applied Physics 52 (11), 113001, 2019
1362019
Fully parallel write/read in resistive synaptic array for accelerating on-chip learning
L Gao, IT Wang, PY Chen, S Vrudhula, J Seo, Y Cao, TH Hou, S Yu
Nanotechnology 26 (45), 455204, 2015
1362015
A ferroelectric field effect transistor based synaptic weight cell
M Jerry, S Dutta, A Kazemi, K Ni, J Zhang, PY Chen, P Sharma, S Yu, ...
Journal of Physics D: Applied Physics 51 (43), 434001, 2018
1332018
Fully parallel RRAM synaptic array for implementing binary neural network with (+ 1,− 1) weights and (+ 1, 0) neurons
X Sun, X Peng, PY Chen, R Liu, J Seo, S Yu
2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 574-579, 2018
1042018
Understanding the resistive switching characteristics and mechanism in active SiOx-based resistive switching memory
YF Chang, PY Chen, B Fowler, YT Chen, F Xue, Y Wang, F Zhou, JC Lee
Journal of Applied Physics 112 (12), 2012
972012
Programming protocol optimization for analog weight tuning in resistive memories
L Gao, PY Chen, S Yu
IEEE Electron Device Letters 36 (11), 1157-1159, 2015
962015
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip
PY Chen, D Kadetotad, Z Xu, A Mohanty, B Lin, J Ye, S Vrudhula, J Seo, ...
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 854-859, 2015
952015
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