| Cache-conscious wavefront scheduling TG Rogers, M O'Connor, TM Aamodt 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 72-83, 2012 | 504 | 2012 |
| VIS speeds new media processing M Tremblay, JM O'Connor, V Narayanan, L He IEEE micro 16 (4), 10-20, 1996 | 420 | 1996 |
| Picojava: A direct execution engine for java bytecode H McGhan, M O'Connor Computer 31 (10), 22-30, 1998 | 266 | 1998 |
| picoJava-I: The Java virtual machine in hardware JM O'Connor, M Tremblay Micro, IEEE 17 (2), 45-53, 1997 | 241 | 1997 |
| Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems K Hsieh, E Ebrahimi, G Kim, N Chatterjee, M O’Connor, N Vijaykumar, ... | 226 | 2016 |
| Cache coherence for GPU architectures I Singh, A Shriraman, WWL Fung, M O'Connor, TM Aamodt 2013 IEEE 19th International Symposium on High Performance Computer …, 2013 | 183 | 2013 |
| Divergence-aware warp scheduling TG Rogers, M O'Connor, TM Aamodt Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013 | 169 | 2013 |
| Understanding reduced-voltage operation in modern DRAM devices: Experimental characterization, analysis, and mechanisms KK Chang, AG Yağlıkçı, S Ghose, A Agrawal, N Chatterjee, A Kashyap, ... Proceedings of the ACM on Measurement and Analysis of Computing Systems 1 (1 …, 2017 | 162 | 2017 |
| Page placement strategies for GPUs within heterogeneous memory systems N Agarwal, D Nellans, M Stephenson, M O'Connor, SW Keckler Proceedings of the Twentieth International Conference on Architectural …, 2015 | 155 | 2015 |
| Compressing DMA engine: Leveraging activation sparsity for training deep neural networks M Rhu, M O'Connor, N Chatterjee, J Pool, Y Kwon, SW Keckler 2018 IEEE International Symposium on High Performance Computer Architecture …, 2018 | 140 | 2018 |
| Scaling the Power Wall: A Path to Exascale O Villa, DR Johnson, M O’Connor, E Bolotin, D Nellans, J Luitjens, ... Supercomputing, 2014 | 136 | 2014 |
| Processor with accelerated array access bounds checking M Tremblay, JM O'Connor, WN Joy US Patent 6,014,723, 2000 | 135 | 2000 |
| Generation isolation system and method for garbage collection JM O'Connor, M Tremblay, S Vishin US Patent 6,098,089, 2000 | 132 | 2000 |
| Characterizing and evaluating a key-value store application on heterogeneous CPU-GPU systems TH Hetherington, TG Rogers, L Hsu, M O'Connor, TM Aamodt 2012 IEEE International Symposium on Performance Analysis of Systems …, 2012 | 129 | 2012 |
| Instruction folding for a stack-based machine JM O'Connor, M Tremblay US Patent 6,026,485, 2000 | 126 | 2000 |
| Bounded-pause time garbage collection system and method including write barrier associated with source and target instances of a partially relocated object M Tremblay, JM O'Connor, GL Steele Jr, S Vishin, O Agesen, S Heller, ... US Patent 5,873,104, 1999 | 126* | 1999 |
| Fine-grained DRAM: Energy-efficient DRAM for extreme bandwidth systems M O’Connor, N Chatterjee, D Lee, J Wilson, A Agrawal, SW Keckler, ... 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture …, 2017 | 123 | 2017 |
| Bounded-pause time garbage collection system and method including read and write barriers associated with an instance of a partially relocated object M Tremblay, JM O'Connor, GL Steele Jr., S Vishin, O Agesen, S Heller, ... US Patent 5,857,210, 1999 | 121* | 1999 |
| A mostly-clean DRAM cache for effective hit speculation and self-balancing dispatch J Sim, GH Loh, H Kim, M OConnor, M Thottethodi 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 247-257, 2012 | 118 | 2012 |
| Write barrier system and method for trapping garbage collection page boundary crossing pointer stores JM O'Connor, M Tremblay, S Vishin US Patent 5,845,298, 1998 | 112 | 1998 |
Gabriel H. LohAMD ResearchVerified email at amd.com
