Ardavan Pedram
Title
Cited by
Cited by
Year
EIE: Efficient inference engine on compressed deep neural network
S Han, X Liu, H Mao, J Pu, A Pedram, MA Horowitz, WJ Dally
ACM SIGARCH Computer Architecture News 44 (3), 243-254, 2016
18302016
Plasticine: A Reconfigurable Architecture For Parallel Patterns
R Prabhakar, Y Zhang, D Koeplinger, M Feldman, T Zhao, S Hadjis, ...
44th International Symposium on Computer Architecture (ISCA 2017), 2017
1042017
Spatial: A language and compiler for application accelerators
D Koeplinger, M Feldman, R Prabhakar, Y Zhang, S Hadjis, R Fiszel, ...
Proceedings of the 39th ACM SIGPLAN Conference on Programming Language …, 2018
762018
Dark memory and accelerator-rich system optimization in the dark silicon era
A Pedram, S Richardson, S Galal, S Kvatinsky, M Horowitz
IEEE Design & Test 34 (2), 39-50, 2017
752017
Codesign Tradeoffs for High-Performance, Low-Power Linear Algebra Architectures
A Pedram, A Gerstlauer, RA van de Geijn
IEEE Transactions on Computers 61 (12), 1724 - 1736, 2012
682012
A systematic approach to blocking convolutional neural networks
X Yang, J Pu, BB Rister, N Bhagdikar, S Richardson, S Kvatinsky, ...
arXiv preprint arXiv:1606.04209, 2016
432016
Local linear model tree (LOLIMOT) reconfigurable parallel hardware
A Pedram, MR Jamali, T Pedram, SM Fakhraie, C Lucas
International Journal of Applied Science, Engineering and Technology 1, 1, 2006
322006
A high-performance, low-power linear algebra core
A Pedram, A Gerstlauer, RA Van De Geijn
Application-Specific Systems, Architectures and Processors (ASAP), 2011 IEEE …, 2011
302011
Evaluating Programmable Architectures for Imaging and Vision Applications
A Vasilyev, N Bhagdikar, A Pedram, S Richardson, S Kvatinsky, ...
IEEE/ACM International Symposium on Microarchitecture, 2016
262016
Deep compression and EIE: Efficient inference engine on compressed deep neural network.
S Han, X Liu, H Mao, J Pu, A Pedram, M Horowitz, B Dally
Hot Chips Symposium, 1-6, 2016
252016
Modeling cache effects at the transaction level
A Pedram, D Craven, A Gerstlauer
International Embedded Systems Symposium, 89-101, 2009
252009
A Linear Algebra Core Design For Efficient Level-3 BLAS
A Pedram, SZ Gilani, NS Kim, R van de Geijn, M Schulte, A Gerstlauer
Application-Specific Systems, Architectures and Processors (ASAP), 2012 IEEE …, 2012
212012
CATERPILLAR: Coarse Grain Reconfigurable Architecture for Accelerating the Training of Deep Neural Networks
Y Li, A Pedram
The 28th Annual IEEE International Conference on Application-specific …, 2017
202017
Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix Factorization Accelerator
A Pedram, A Gerstlauer, RA van de Geijn
202014
Distributing congestions in NOCs through a dynamic routing algorithm based on input and output selections
M Daneshtalab, A Pedram, MH Neishaburi, M Riazati, A Afzali-Kusha, ...
VLSI Design, 2007. Held jointly with 6th International Conference on …, 2007
172007
Floating Point Architecture Extensions for Optimized Matrix Factorization
A Pedram, A Gerstlauer, RA van de Geijn
132013
On the efficiency of register file versus broadcast interconnect for collective communications in data-parallel hardware accelerators
A Pedram, A Gerstlauer, RA Van De Geijn
2012 IEEE 24th International Symposium on Computer Architecture and High …, 2012
132012
A Highly Efficient Multicore Floating-Point FFT Architecture Based on Hybrid Linear Algebra/FFT Cores
A Pedram, JD McCalpin, A Gerstlauer
Journal of Signal Processing Systems, 2014
122014
Transforming A Linear Algebra Core to An FFT Accelerator
A Pedram, J McCalpin, A Gerstlauer
Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE …, 2013
112013
Improving Energy Efficiency of DRAM by Exploiting Half Page Row Access
H Ha, A Pedram, S Richardson, S Kvatinsky, M Horowitz
IEEE/ACM International Symposium on Microarchitecture, 2016
72016
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