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Jedrzej Solecki
Jedrzej Solecki
Mentor, A Siemens Business
Verified email at mentor.com
Title
Cited by
Cited by
Year
Low-power programmable PRPG with test compression capabilities
M Filipek, G Mrugalski, N Mukherjee, B Nadeau-Dostie, J Rajski, J Solecki, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (6 …, 2014
482014
Trimodal scan-based test paradigm
G Mrugalski, J Rajski, J Solecki, J Tyszer, C Wang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (3 …, 2016
362016
Logic BIST With Capture-Per-Clock Hybrid Test Points
E Moghaddam, N Mukherjee, J Rajski, J Solecki, J Tyszer, J Zawada
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
302018
Full-scan LBIST with capture-per-cycle hybrid test points
S Milewski, N Mukherjee, J Rajski, J Solecki, J Tyszer, J Zawada
2017 IEEE International Test Conference (ITC), 1-9, 2017
182017
Deterministic built-in self-test based on compressed test patterns stored on chip and their derivatives
G Mrugalski, J Rajski, L Rybak, J Solecki, J Tyszer
US Patent 9,933,485, 2018
162018
Deterministic Built-In Self-Test
G Mrugalski, J Rajski, L Rybak, J Solecki, J Tyszer
US Patent App. 15/051,063, 2016
16*2016
Staggered ATPG with capture-per-cycle observation test points
Y Liu, J Rajski, SM Reddy, J Solecki, J Tyszer
2018 IEEE 36th VLSI Test Symposium (VTS), 1-6, 2018
132018
Low power programmable PRPG with enhanced fault coverage gradient
J Solecki, J Tyszer, G Mrugalski, N Mukherjee, J Rajski
2012 IEEE International Test Conference, 1-9, 2012
132012
Time and Area Optimized Testing of Automotive ICs
N Mukherjee, D Tille, M Sapati, Y Liu, J Mayer, S Milewski, E Moghaddam, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (1), 76-88, 2020
122020
Test Time and Area Optimized BrST Scheme for Automotive ICs
N Mukherjee, D Tille, M Sapati, Y Liu, J Mayer, S Milewski, E Moghaddam, ...
2019 IEEE International Test Conference (ITC), 1-10, 2019
122019
Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns
G Mrugalski, J Rajski, Ł Rybak, J Solecki, J Tyszer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
112017
Test-per-clock based on dynamically-partitioned reconfigurable scan chains
J Rajski, J Solecki, J Tyszer, G Mrugalski
US Patent App. 15/150,147, 2016
112016
TestExpress-New Time-Effective Scan-Based Deterministic Test Paradigm
G Mrugalski, J Rajski, J Solecki, J Tyszer, C Wang
2015 IEEE 24th Asian Test Symposium (ATS), 19-24, 2015
112015
Test-per-clock based on dynamically-partitioned reconfigurable scan chains
J Rajski, J Solecki, J Tyszer, G Mrugalski
US Patent 9,335,377, 2016
102016
Test-Per-Clock Based On Dynamically-Partitioned Reconfigurable Scan Chains
J Rajski, J Solecki, J Tyszer, G Mrugalski
US Patent App. 13/919,974, 2014
102014
Fault diagnosis with orthogonal compactors in scan-based designs
B Benware, G Mrugalski, A Pogiel, J Rajski, J Solecki, J Tyszer
Journal of Electronic Testing 27 (5), 599-609, 2011
92011
Fault-driven scan chain configuration for test-per-clock
J Rajski, J Solecki, J Tyszer, G Mrugalski
US Patent 9,003,248, 2015
72015
Fault-driven scan chain configuration for test-per-clock
J Rajski, J Solecki, J Tyszer, G Mrugalski
US Patent App. 13/919,998, 2014
72014
Test application time reduction using capture-per-cycle test points
J Rajski, S Milewski, N Mukherjee, J Solecki, J Tyszer, J Zawada
US Patent 10,509,072, 2019
62019
Diagnosis of failing scan cells through orthogonal response compaction
B Benware, G Mrugalski, A Pogiel, J Rajski, J Solecki, J Tyszer
2010 15th IEEE European Test Symposium, 221-226, 2010
62010
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