Jie Han
Jie Han
Universities of Alberta, Florida, Delft and Tsinghua
Vahvistettu sähköpostiosoite verkkotunnuksessa - Kotisivu
Approximate computing: An emerging paradigm for energy-efficient design
J Han, M Orshansky
2013 18th IEEE European Test Symposium (ETS), 1-6, 2013
New metrics for the reliability of approximate and probabilistic adders
J Liang, J Han, F Lombardi
IEEE Transactions on computers 62 (9), 1760-1771, 2012
Design and analysis of approximate compressors for multiplication
A Momeni, J Han, P Montuschi, F Lombardi
IEEE Transactions on Computers 64 (4), 984-994, 2014
A low-power, high-performance approximate multiplier with configurable partial error recovery
C Liu, J Han, F Lombardi
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014
Approximate XOR/XNOR-based adders for inexact computing
Z Yang, A Jain, J Liang, J Han, F Lombardi
2013 13Th IEEE international conference on nanotechnology (IEEE-NANO 2013 …, 2013
Design of approximate radix-4 booth multipliers for error-tolerant computing
W Liu, L Qian, C Wang, H Jiang, J Han, F Lombardi
IEEE Transactions on computers 66 (8), 1435-1441, 2017
A review, classification, and comparative evaluation of approximate arithmetic circuits
H Jiang, C Liu, L Liu, F Lombardi, J Han
ACM Journal on Emerging Technologies in Computing Systems (JETC) 13 (4), 1-34, 2017
A system architecture solution for unreliable nanoelectronic devices
J Han, P Jonker
IEEE Transactions on Nanotechnology 1 (4), 201-208, 2002
Approximate radix-8 booth multipliers for low-power and high-performance operation
H Jiang, J Han, F Qiao, F Lombardi
IEEE Transactions on Computers 65 (8), 2638-2644, 2015
A comparative review and evaluation of approximate adders
H Jiang, J Han, F Lombardi
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 343-348, 2015
Approximate arithmetic circuits: A survey, characterization, and recent applications
H Jiang, FJH Santiago, H Mo, L Liu, J Han
Proceedings of the IEEE 108 (12), 2108-2135, 2020
Toward hardware-redundant, fault-tolerant logic for nanoelectronics
J Han, J Gao, P Jonker, Y Qi, JAB Fortes
IEEE Design & Test of Computers 22 (4), 328-339, 2005
A survey of coarse-grained reconfigurable architecture and design: Taxonomy, challenges, and applications
L Liu, J Zhu, Z Li, Y Lu, Y Deng, J Han, S Yin, S Wei
ACM Computing Surveys (CSUR) 52 (6), 1-39, 2019
Reliability evaluation of logic circuits using probabilistic gate models
J Han, H Chen, E Boykin, J Fortes
Microelectronics Reliability 51 (2), 468-476, 2011
Low-power approximate multipliers using encoded partial products and approximate compressors
MS Ansari, H Jiang, BF Cockburn, J Han
IEEE journal on emerging and selected topics in circuits and systems 8 (3 …, 2018
A stochastic computational approach for accurate and efficient reliability evaluation
J Han, H Chen, J Liang, P Zhu, Z Yang, F Lombardi
IEEE Transactions on Computers 63 (6), 1336-1350, 2012
Design and evaluation of multiple valued logic gates using pseudo N-type carbon nanotube FETs
J Liang, L Chen, J Han, F Lombardi
IEEE Transactions on Nanotechnology 13 (4), 695-708, 2014
Approximate compressors for error-resilient multiplier design
Z Yang, J Han, F Lombardi
2015 IEEE international symposium on defect and fault tolerance in VLSI and …, 2015
A defect-and fault-tolerant architecture for nanocomputers
J Han, P Jonker
Nanotechnology 14 (2), 224, 2003
A survey of stochastic computing neural networks for machine learning applications
Y Liu, S Liu, Y Wang, F Lombardi, J Han
IEEE Transactions on Neural Networks and Learning Systems 32 (7), 2809-2824, 2020
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Artikkelit 1–20