Comprehensive study of soft errors in advanced CMOS circuits with 90/130 nm technology Y Tosaka, H Ehara, M Igeta, T Uemura, H Oka, N Matsuoka, K Hatanaka
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004
89 2004 SEILA: Soft error immune latch for mitigating multi-node-SEU and local-clock-SET T Uemura, Y Tosaka, H Matsuyama, K Shono, CJ Uchibori, K Takahisa, ...
2010 IEEE International Reliability Physics Symposium, 218-223, 2010
58 2010 Multi-scale Monte Carlo simulation of soft errors using PHITS-HyENEXSS code system S Abe, Y Watanabe, N Shibano, N Sano, H Furuta, M Tsutsui, T Uemura, ...
IEEE Transactions on Nuclear Science 59 (4), 965-970, 2012
42 2012 Reliability characterization of 10nm FinFET technology with multi-VT gate stack for low power and high performance M Jin, C Liu, J Kim, J Kim, H Shim, K Kim, G Kim, S Lee, T Uemura, ...
2016 IEEE International Electron Devices Meeting (IEDM), 15.1. 1-15.1. 4, 2016
33 2016 Neutron-induced soft-error simulation technology for logic circuits T Uemura, Y Tosaka, S Satoh
Japanese journal of applied physics 45 (4S), 3256, 2006
31 2006 Neutron-induced soft-error simulation technology for logic circuits T Uemura, Y Tosaka, S Satoh
Japanese journal of applied physics 45 (4S), 3256, 2006
31 2006 Soft-error in SRAM at ultra-low voltage and impact of secondary proton in terrestrial environment T Uemura, T Kato, H Matsuyama, M Hashimoto
IEEE Transactions on Nuclear Science 60 (6), 4232-4237, 2013
25 2013 The 10th generation 16-core sparc64™ processor for mission critical unix server R Kan, T Tanaka, G Sugizaki, K Ishizaka, R Nishiyama, S Sakabayashi, ...
IEEE Journal of Solid-State Circuits 49 (1), 32-40, 2013
25 2013 A 10th generation 16-core SPARC64 processor for mission-critical UNIX server R Kan, T Tanaka, G Sugizaki, R Nishiyama, S Sakabayashi, Y Koyanagi, ...
2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013
25 2013 Angular dependency of neutron-induced multiple cell upsets in 65-nm 10T subthreshold SRAM R Harada, SI Abe, H Fuketa, T Uemura, M Hashimoto, Y Watanabe
IEEE Transactions on Nuclear Science 59 (6), 2791-2795, 2012
25 2012 Investigation of logic circuit soft error rate (SER) in 14nm FinFET technology T Uemura, S Lee, J Park, S Pae, H Lee
2016 IEEE International Reliability Physics Symposium (IRPS), 3B-4-1-3B-4-4, 2016
24 2016 Neutron-induced soft error analysis in MOSFETs from a 65nm to a 25 nm design rule using multi-scale Monte Carlo simulation method S Abe, Y Watanabe, N Shibano, N Sano, H Furuta, M Tsutsui, T Uemura, ...
2012 IEEE International Reliability Physics Symposium (IRPS), SE. 3.1-SE. 3.6, 2012
23 2012 Measurement of neutron-induced single event transient pulse width narrower than 100ps H Nakamura, K Tanaka, T Uemura, K Takeuchi, T Fukuda, S Kumashiro
2010 IEEE International Reliability Physics Symposium, 694-697, 2010
22 2010 Scaling effect and circuit type dependence of neutron induced single event transient H Nakamura, T Uemura, K Takeuchi, T Fukuda, S Kumashiro, T Mogami
2012 IEEE International Reliability Physics Symposium (IRPS), 3C. 3.1-3C. 3.7, 2012
20 2012 Using low pass filters in mitigation techniques against single-event transients in 45nm technology LSIs T Uemura, R Tanabe, Y Tosaka, S Satoh
2008 14th IEEE International On-Line Testing Symposium, 117-122, 2008
19 2008 Technology Scaling Trend of Soft Error Rate in Flip-Flops in nm Bulk FinFET Technology T Uemura, S Lee, U Monga, J Choi, S Lee, S Pae
IEEE Transactions on Nuclear Science 65 (6), 1255-1263, 2018
17 2018 Reliability of 8Mbit embedded-STT-MRAM in 28nm FDSOI technology Y Ji, HJ Goo, J Lim, SB Lee, S Lee, T Uemura, JC Park, SI Han, SC Shin, ...
2019 IEEE International Reliability Physics Symposium (IRPS), 1-3, 2019
16 2019 Investigation of alpha-induced single event transient (SET) in 10 nm FinFET logic circuit T Uemura, S Lee, D Min, I Moon, J Lim, S Lee, HC Sagong, S Pae
2018 IEEE International Reliability Physics Symposium (IRPS), P-SE. 1-1-P-SE …, 2018
15 2018 Origin analysis of thermal neutron soft error rate at nanometer scale T Yamazaki, T Kato, T Uemura, H Matsuyama, Y Tada, K Yamazaki, ...
Journal of Vacuum Science & Technology B 33 (2), 2015
14 2015 Study on influence of device structure dimensions and profiles on charge collection current causing SET pulse leading to soft errors in logic circuits K Tanaka, H Nakamura, T Uemura, K Takeuchi, T Fukuda, S Kumashiro
2009 International Conference on Simulation of Semiconductor Processes and …, 2009
14 2009